Semiconductor device, image display device, and method and apparatus for manufacture thereof

ABSTRACT

A switch device includes a source, a drain, and a gate electrode which are conductive, one or more semiconductor island layer(s) formed between the source and drain, an insulating film between the source and island layer, an insulating film between the drain and island layer, an insulating layer between island layers if a plurality of island layers are provided, and a gate capacitor formed by the gate electrode, at least one island layer, and a gate insulating film provided between the gate electrode and the island layer. The electric field applied to the gate capacitor is set to be substantially parallel with a channel current flowing via the island between the source and the drain.

TECHNICAL FIELD

The present invention relates to a semiconductor device, an imagedisplay device, and method and apparatus for manufacturing the imagedisplay device and relates to a technique effective for use in a devicehaving a switching device in which a leak current in an off state isreduced.

BACKGROUND ART

FIG. 15 shows an example of a pixel configuration in a TFT(Thin-Film-Transistor) liquid crystal panel according to a conventionaltechnique. Each pixel is constructed by a pixel switch 101, aliquid-crystal capacitor 102, and a load capacitor 103. One end of thepixel switch 101 is connected in parallel with the liquid-crystalcapacitor 102 and the load capacitor 103. The other end of the pixelswitch 101 is connected to a signal-line driving circuit 107 via asignal line 106. The gate of the pixel switch 101 is connected to agate-line driving circuit 108 via a gate line 104. The other end of theload capacitor 103 is connected to a load capacitor line 105. Althoughnot shown, pixels are arranged in a matrix on a panel, the signal line106 is connected commonly to pixels in the column direction, and thegate line 104 and the load capacitor line 105 are connected commonly topixels in the row direction.

In FIG. 15, at the beginning of a horizontal scanning period, a pixelrow to which a display signal is to be written is selected in apredetermined order by the gate-line driving circuit 108, and the pixelswitch 101 of this row is set in the on state. Subsequently, thesignal-line driving circuit supplies the write signal to each of thepixels in the selected row to the liquid-crystal capacitor 102 and theload capacitor 103 via the signal line 106 and the pixel switch 101. Atthe end of the horizontal scanning period, the gate-line driving circuit108 sets the pixel switch 101 of the row into the off state, therebyfinishing the writing operation on the pixels of one row.

FIG. 16 is a sectional structural diagram of a polycrystal TFT as acomponent of the pixel switch 101. The channel portion is constructed bya poly-Si thin film. On the poly-Si thin film, a gate electrode 112 isprovided via a gate insulating film 115. A source 110 and a drain 111are formed by doping an n-type high-concentration impurity into thepoly-Si thin film. Further, n-regions 113 and 114 for electric fieldreduction are provided so as to be self-aligned with the gate insulatingfilm 115.

FIG. 17 shows the current-voltage characteristics of the polycrystal TFTas a component of the pixel switch 101. When a gate voltage Vgs becomesnegative and the pixel switch 101 is turned off, it is ideal that acurrent Ids becomes 0. However, in reality, as the gate voltage Vgsincreases on the negative side, the off characteristic of thepolycrystal TFT indicates an increase tendency as shown by the arrow inFIG. 17. This is caused by thermal carrier emission from defect-inducedstates in the poly-Si film and occurrence of a leak current bytunneling. The details of such a leak current are described in, forexample, “Journal of Applied Physics”, 50(8), pp. 5484-5487 (1979).

In the case where the leak current cannot be ignored, a signal chargewritten in the liquid-crystal capacitor 102 flows out from the pixelswitch 101, so that deterioration occurs in a displayed image due toflicker noise or the like. The purpose of providing the n-regions 113and 114 for electric field reduction in the pixel switch 101 is toreduce the leak current. Further, the purpose of providing the loadcapacitor 103 for a pixel is to suppress the influence of the leakcurrent by increasing the amount of charges written into the pixel.

Such a conventional technique is described in, for example, “Proceedingsof International Display Workshop '96 (IDW'96)”, pp. 5-8 (1996).

In order to reduce the influence of the leak current of the pixel switch101 to a level at which the influence can be ignored, employment of onlythe n-regions 113 and 114 is insufficient, and the load capacitor 103has to be formed. However, when the pixel size decreases as the liquidcrystal panel is becoming more precise, by providing the load capacitor103, the fill-factor of pixels deteriorates, and a problem such that thebrightness of the screen is reduced occurs.

It is therefore an object of the invention to provide a semiconductordevice having a high-performance novel switching device in which a leakcurrent in an off state is reduced. Another object is to provide animage display device realizing higher definition by using the switchdevice. Further another object is to provide method and apparatus formanufacturing a semiconductor device including the switch device and asemiconductor device suitable for forming the image display device. Theabove and other objects and novel features of the invention will becomeapparent from the description of the specification and the appendeddrawings.

DISCLOSURE OF THE INVENTION

Outline of a representative embodiment of the invention disclosed in thespecification will be briefly described as follows. A switch deviceincludes conductive source, drain, and gate electrode, one or moresemiconductor island layer(s) formed between the source and drain, aninsulating film between the source and island layer, an insulating filmbetween the drain and island layer, an insulating layer between islandlayers if a plurality of island layers are provided, and a gatecapacitor formed by the gate electrode, at least one island layer, and agate insulating film provided between the gate electrode and the islandlayer. The electric field applied to the gate capacitor is set to besubstantially parallel with a channel current flowing via the islandbetween the source and the drain.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional structural diagram showing an example of a switchdevice according to the invention.

FIGS. 2A and 2B are diagrams for explaining the operation of the switchdevice shown in FIG. 1.

FIG. 3 is a block diagram showing an example of an image display deviceconstructed by using the switch device according to the invention.

FIG. 4 is a schematic cross section of a pixel cell in the image displaydevice.

FIG. 5 is a current-voltage characteristic diagram of a pixel switchingdevice used for the pixel cell.

FIG. 6 is a sectional structural diagram showing another example of thepixel switch used for the image display device.

FIGS. 7A and 7B are diagrams for explaining a method of manufacturingthe pixel switch shown in FIG. 6.

FIG. 8 is a diagram showing the configuration of an apparatus formanufacturing an image display device including the pixel switchillustrated in FIG. 6.

FIGS. 9A and 9B are diagrams for explaining another example of the pixelswitch according to the invention.

FIGS. 10A and 10B are diagrams for explaining the operation of the pixelswitch shown in FIGS. 9A and 9B.

FIG. 11 is a sectional structural diagram showing an example of a pixelswitch for use in the image display device and a device as a componentof a gate-line driving circuit and a signal-line driving circuit.

FIG. 12 is a sectional structural diagram showing another example of apixel switch for use in the image display device and a device as acomponent of a gate-line driving circuit and a signal-line drivingcircuit.

FIG. 13 is a sectional structural diagram showing further anotherexample of the switch device according to the invention.

FIG. 14 is a schematic circuit diagram showing an example of a DRAM chipusing the switch device according to the invention.

FIG. 15 is a configuration diagram showing an example of a TFT liquidcrystal panel according to a conventional technique.

FIG. 16 is a sectional structural diagram showing an example of apolycrystal TFT as a component of a pixel switch according to theconventional technique.

FIG. 17 is a current-voltage characteristic diagram of the polycrystalTFT as a component of the pixel switch according to the conventionaltechnique.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention will be described in more detail with reference to theappended drawings.

FIG. 1 is a schematic sectional structural diagram showing an example ofa switch device according to the invention. The channel portion isconstructed by poly-Si islands 14 and 15. An island denotes anisland-shaped layer isolated from other semiconductor layers and thelike by an insulating film and is a term generally used in,particularly, a TFT liquid crystal display panel and the like. A source10 and a drain 11 of the switch device are formed by doping phosphorusas an n-type high-concentration impurity into the poly-Si thin film. Inthe switch device according to the invention similar to an MOSstructure, a current is passed bidirectionally as in a known MOStransistor or TFT. The source and the drain of the switch device aretherefore determined according to the application direction of thevoltage. In the specification, for convenience, the lower conductivelayer is called a source (SD1) 10 and the upper conductive layer iscalled a drain (SD2) 11.

Between the source 10 and the poly-Si island 15, an insulating film 13 ais formed. Between the poly-Si islands 15 and 14, an insulating film 13b is formed. Between the poly-Si island 14 and the drain 11, aninsulating film 13 c is formed. Further, on the poly-Si island 14,although not limited, a gate electrode (G) 12 is provided via theinsulating film 13 c and a gate insulating film 13 d. The switch deviceis formed on the surface of a flat substrate 60 which is a propersemiconductor substrate or insulating substrate.

The operation of the switch device will be described hereinbelow byreferring to FIGS. 2A and 2B. FIGS. 2A and 2B are diagrams showingpotentials of the source 10, poly-Si islands 15 and 14, and drain 11.The potential increases with a distance from the upper side as shown bythe arrow. FIG. 2A corresponds to a gate on state, and FIG. 2Bcorresponds to a gate off state.

When a proper first voltage is applied to the gate electrode 12 and thegate electrode 12 enters the on state shown in FIG. 2A, the potential inthe poly-Si island 14 increases by capacitive coupling between the gateelectrode 12 and a parasitic capacitance C1 also shown in FIG. 1 and,further, the potential of the poly-Si island 15 also increases bycapacitive coupling of a parasite capacitance C2 between the poly-Siislands 14 and 15. Since each of the insulating film 13 a and 13 c isset to 3 nm in which a tunneling current occurs and each of the poly-Siislands 15 and 14 is set to 5 nm smaller than an electronmean-free-path, electrons charged in the poly-Si island 15 from thesource 10 pass through the central insulating film 13 b of whichpotential is increased and flows in the drain 11 while the electrons arehardly scattered. When the potential in the source 10 and that in drain11 finally become equal to each other, the channel current reachesequilibrium and the channel current seemingly stops. Since the thicknessof the gate insulating film 13 d is 20 nm and is relatively large,generation of the gate current can be almost ignored.

Subsequently, when a second voltage is applied to the gate electrode 12and the gate electrode 12 enters an off state shown in FIG. 2B, thepotential in the poly-Si islands 15 and 14 decreases due to capacitivecoupling with the gate electrode 12. When seen from the source 10, aplurality of tunnel barriers including the insulating film 13 b in thecenter are generated in the channel. In this case, by the effect of theplurality of tunnel barriers, the leak current between the source 10 andthe drain 11 can be reduced to an extremely small value.

Refer to Japanese Unexamined Patent Application Publication (JP-A) No.10-200001 for the details of the basic operation principle of the switchdevice, that is, the operation principle such that the potential of thepoly-Si islands 15 and 14 is changed by the gate electrode and thechannel current is switched by using the poly-Si islands 15 and 14 aschannels.

The switch device of the example is devised by forming the gateelectrode so that the gate capacitance becomes substantially parallelwith the channel current flowing between the source and drain via theislands. The switch device of the example is substantially differentfrom the invention of JP-A-10-200001 with respect to a point that theTFT operation can be realized without performing a fine photoresistetching process, a point that a heavy current can be obtained bycontrolling the potential of the whole poly-Si island by the capacitivecoupling with the gate, and the like.

Specifically, in the case of using the switch device also as a pixelswitch of a TFT liquid crystal panel as will be described herein later,when a device is formed on a silicon substrate as a precondition likeJP-A-10-200001, due to large substrate dimension, the device process onthe large-size TFT liquid crystal panel with fine photoresist etching asin the case using the silicon substrate is substantially impossible.Consequently, the device structure as in the invention considering thatpoint as well is extremely useful.

FIG. 3 is a block diagram showing an example of an image display deviceconstructed by using the switch device according to the invention. Thediagram shows an example of the pixel configuration of a TFT liquidcrystal panel. In broad outline, the switch device according to theinvention is used as a pixel switch (hereinbelow, called a TFT) and eachpixel is constructed by the TFT and a liquid-crystal capacitor CLC. Oneend of the pixel switch TFT is connected to a pixel electrode of theliquid-crystal capacitor CLC, and the other end is connected to asignal-line driving circuit DDV via a signal line Y1, and the gate ofthe pixel switch TFT is connected to a gate-line (scanning line) drivingcircuit CDV via a scanning line X1. In the diagram, three signal linesY1 to Y3, three scanning lines X1 to X3, and pixel cells provided at theintersecting points of the signal lines Y1 to Y3 and the three scanninglines X1 to X3 and each constructed by the pixel switch TFT and theliquid crystal capacitor CLC are illustrated representatively. Thecircuits are formed on a single glass substrate.

The signal line electrodes Y1 to Y3 of the liquid crystal display panelare driven by the display driver (signal line driving circuit) DDV. Eachof the signal line electrodes Y1 to Y3 is connected to one of sourcesand drain of the pixel switch TFT. The liquid crystal capacitor CLC as apixel is connected to the other source and drain of the pixel switchTFT.

The gate line (scanning line) electrodes X1 to X3 to which gates of thepixel switches TFT are connected are connected to the scanning linedriving circuit CDV. The scanning line driving circuit CDV sequentiallyselects the scanning line electrodes X1 to X3 synchronously with atiming signal CL1. When the scanning line electrode X1 is set to thehigh level, the pixel switch TFT in the first row is turned on, and adisplay signal corresponding to a signal-stepping voltage output fromthe signal line electrodes Y1 to Y3 is held in the liquid-crystalcapacitor CLC.

After that, the scanning line electrodes X2 and X3 are sequentiallyselected and, synchronously with the selecting operation, a displaysignal as described above is output from the display driver DDV and heldin each liquid crystal capacitor CLC. The vertical shift clock VCK issynchronized with the timing signal CL1. To a common electrode COM ofthe liquid crystal display panel, a bias voltage VCOM is supplied.

The signal-line driving circuit DDV is provided with a voltage followercircuit to which signal-stepping voltages such as V1 to Vn (V1+, V1−,V2+, V2−, . . . , Vn+, Vn−) are supplied. The signal-line drivingcircuit DDV decodes pixel data DATA input synchronously with a timingsignal CL2, selects a signal-stepping voltage output from the voltagefollower circuit in correspondence with pixel data, and outputs theselected signal-stepping voltage to the signal lines Y1 to Y3.

The signal line driving circuit DDV may receive a serial analog signalor a display signal in the form of the signal-stepping voltage,sequentially select the signal lines Y1 to Y3, and sequentially writethe display signal to the pixels selected by the scanning line X1. Inother words, in a manner similar to a raster scanning operation of aCRT, display signals serially input may be written in correspondingliquid crystal pixels in a time sequential matter.

An AC-driving signal M is used to reverse the polarities of the writevoltages so as to prevent application of a direct current to the liquidcrystal pixel. Specifically, when a display operation of one screen isfinished, the polarities of voltages written in the liquid crystal pixelare reversed by the AC-driving signal M around the common voltage VCOMas a center, thereby AC-driving the liquid crystal as a whole. Forexample, in the first display period (frame), a negative voltage issupplied to liquid crystals corresponding to odd-numbered scanninglines, and a positive voltage is supplied to liquid crystalscorresponding to even-numbered scanning lines. In the next frame, incontrast to the above, the positive voltage is supplied to the liquidcrystals corresponding to the odd-numbered scanning lines and thenegative voltage is supplied to liquid crystals corresponding to theeven-numbered scanning lines.

FIG. 4 is a schematic cross section showing an example of a pixel cellin the image display device. As the pixel switch, the switch deviceshown in FIG. 1 is used as it is. In the example, the conductive layer10 described as the source is used as the signal line Y and extends inthe direction perpendicular to the face of the drawing sheet. The gateelectrode 12 is used as the scanning line X and extends in the lateraldirection of the drawing. The conductive layer 11 described as the drainis connected to a liquid crystal pixel electrode 16. The pixel electrodeis formed by an ITO film as a transparent electrode.

In the liquid crystal display panel, although not limited, an uppertransparent glass substrate (not shown) is provided so as to face theglass substrate on which the pixel switch (TFT) and the pixel electrode16 are provided. On the upper transparent glass substrate, a colorfilter, a black matrix pattern for optical shield, and a commonelectrode are formed.

Although not limited, on the surface of each of the upper and lowerglass substrates, a silicon oxide film is formed by a dipping process orthe like. Consequently, even if there is a sharp scratch in the surfaceof the transparent glass substrate, it can be covered with the siliconoxide film, so that a signal line electrode, a shield film, and the likedeposited on the surface can be maintained uniform.

FIG. 5 shows the current-voltage characteristics of the pixel switch. Byusing the switch device according to the invention as theabove-described pixel switch, when the gate voltage becomes negative andthe pixel switch TFT is turned off, the current becomes almost zero. Asshown in FIG. 3, therefore, in the example, even if a load capacitor isnot provided for the pixel, deterioration in a display image due toflicker noise or the like caused by a leak current in the pixel switchdoes not occur.

By the effect, in the image display device of the example, even when thepixel size is reduced as the resolution of the liquid crystal panelbecomes higher, a problem such that the fill-factor of pixels decreasesdue to the existence of the load capacitor and the brightness of thescreen decreases does not occur. Thus, the image displaying operationcan be realized with high definition and high quality.

In the example, in order to reduce the resistance value in the switchdevice, an n-type impurity is lightly doped in the poly-Si islands 14and 15. However, when the concentration of the n-type impurity isincreased too much, the mean-free-path of an electron in the poly-Siislands becomes shorter, and it causes decrease in an on-current.Therefore, the concentration of the n-type impurity has to be set to10¹⁶ cm⁻³ or lower.

Although the operation speed margin of the switch will be narrowed, thepoly-Si islands 14 and 15 can be made of what is called i-type poly-Si.In the invention, in theory, the poly-Si island can be replaced with asingle crystal Si island having a low impurity concentration.

In the liquid crystal display panel, it is also possible to form thepixel switch (TFT), the pixel electrode 16, a common electrode formedwhile sandwiching a liquid crystal, a color filter, and the like on asingle glass substrate.

The pixel switch has been mainly described above. The image displaydevice of the example is realized by, but not limited, constructing thescanning-line driving circuit CVD and the signal line driving circuitDDV by a poly-Si LSI chip and mounting the resultant on the glasssubstrate 60.

FIG. 6 is a sectional structural diagram showing another example of thepixel switch used in the image display device. A source 20 formed bydoping phosphorus as an n-type high-concentration impurity into thepoly-Si thin film is provided on a source leading electrode 30. On thesource 20, an insulating film 26 a, a poly-Si island 25, an insulatingfilm 26 b, a poly-Si island 24, an insulating film 26 c, and a drain 21formed by doping phosphorus as an n-type high-concentration impurityinto the poly-Si thin film are sequentially formed. On the insulatingfilm 26 c and the drain 21, a gate electrode 22 is provided via a gateinsulating film 26 d. Since the operation of the pixel switch is similarto that already described in the example of FIG. 1, its description willnot be repeated.

FIGS. 7A and 7B are explanatory diagrams for explaining a method ofmanufacturing the pixel switch shown in FIG. 6. First, on a glasssubstrate 31 as an insulating substrate, the source leading electrode 30is processed. On the source leading electrode 30, the poly-Si thin filmlayer in which phosphorus as an n-type high-concentration impurity isdoped is formed in thickness of 50 nm by CVD. Subsequently, an Si3N4insulating layer 26 is similarly formed in 5 nm by CVD, and an amorphousSi layer is formed in 10 nm by CVD. The amorphous Si layer is irradiatedwith a high-energy excimer-laser beam to be converted to the poly-Sithin film layer 25.

In a manner similar to the above, an Si3N4 insulating layer of 5 nm and,further, the poly-Si thin film layer 24 of 10 nm are formed.Subsequently, an Si3N4 insulating layer 28 of 5 nm and the poly-Si thinfilm layer 21 of 50 nm in which phosphorus as an n-typehigh-concentration impurity is doped are formed. The resultant is shownin FIG. 7A.

FIG. 7B shows a state where the multilayer film is patterned in a lumpby dry etching using a photoresist process to thereby form a channelregion in the pixel switch 1. In the structure, a part of the n-typehigh-concentration poly-Si thin film layer 21 is etched, thereby formingthe SiO2 gate insulating film 26 d of 10 nm and a gate electrode 22. Insuch a manner, the pixel switch structure shown in FIG. 6 is completed.Although not shown, formation of a protective film, wiring, and the likeare subsequently conducted.

In order to avoid deterioration in control of film quality due toformation of a natural oxide film on the surface of each of the films,in the invention, the multilayer film is devised to be formed insuccessive processes as will be described hereinbelow.

FIG. 8 is a diagram showing the configuration of an apparatus formanufacturing an image display device including the pixel switchillustrated in FIG. 6. A vacuum chamber body 41 is provided with a CVDsystem 43 for the poly-Si film in which phosphorus as an n-typehigh-concentration impurity is doped, a CVD system 44 for the amorphousSi film, a high-energy excimer-laser exposure-instrument 45, a CVDsystem 46 for the Si3N4 insulating film, and a glass substrate loadingport 42. In the center of the systems, a substrate carrier 47 isprovided. Concretely, the substrate carrier 47 is substantially operatedin vacuum. By employing the apparatus, formation of the multilayer filmis made possible while avoiding generation of a natural oxide film andan influence of a foreign matter in the air.

By employing the manufacturing the method using such a manufacturingapparatus, formation of a natural oxide film and invasion of a foreignmatter on/in the very thin insulating film and the island layer can beprevented. Thus, a desired current in the on state can be obtained, andan ideal switch device in which a leak current is hardly passed in theoff state can be formed. Moreover, in formation of the small electricelement on a large substrate like a liquid crystal display panel ascompared with the semiconductor wafer, since the influence of adhesionof a foreign matter in the air or the like is great, the manufacturingapparatus and method are extremely useful.

In the embodiment, the poly-Si island layer is formed by crystallizingthe amorphous Si film with the high-energy excimer laser beam.Consequently, the excellent polycrystal film having extremely lowdefect-induced-state density can be used for a poly-Si island, and thepixel switch having a low on-state resistance between the source anddrain can be formed.

In the foregoing example, the source 20 and drain 21 are formed by apoly-Si film in which phosphorus as an n-type high-concentrationimpurity is doped. Alternately, a metal layer may be used. What iscalled i-type poly-Si having an impurity concentration in the poly-Siisland lower than the defect-induced-state density is used. As describedabove, it is also possible to use a low-concentration p-type or n-typeimpurity although the mean-free-path of electrons decreases.

Although Si3N4 is used for the insulating film between the poly-Siislands, an effect similar to that in the embodiment can be alsoobtained in theory with another insulating film made of SiO2 or thelike. In the example, an n-type device using the n-typehigh-concentration poly-Si thin film layers 20 and 21 is employed.Alternately, although the voltages are reversed, a p-type device usingp-type high-concentration poly-Si thin film layers 20 and 21 can beemployed.

Although the multilayer film forming apparatus shown in FIG. 8 carriesthe substrate in vacuum between the film forming systems, it is alsopossible to charge N2 or another inert gas into the chamber 41 and carrythe substrate in such an atmosphere.

FIGS. 9A and 9B are diagrams for explaining another example of the pixelswitch according to the invention. FIG. 9A is a sectional structuraldiagram of a transistor device as a component of the pixel switch. FIG.9B is a plan view of the transistor device. On a source 50 obtained bydoping phosphorus as an n-type high-concentration impurity into thepoly-Si thin film, an Si3N4 insulating film 54 a, a poly-Si island 52,an Si3N4 insulating film 54 b, and a drain 51 obtained by dopingphosphorus as an n-type high-concentration impurity into the poly-Sithin film are sequentially formed. As shown in FIG. 9B, the poly-Siisland 52 extends in the lateral direction so as to be deviated from thesource 50 and the drain 51. On the poly-Si island 52, a gate electrode53 is provided via an SiO2 gate insulating film (not shown).

FIGS. 10A and 10B are diagrams for explaining the operation of the pixelswitch illustrated in FIGS. 9A and 9B. FIGS. 10A and 10B show potentialsin the source 50, poly-Si island 52, and drain 51. FIG. 10A correspondsto a state where the gate is on. FIG. 10B corresponds to a state wherethe gate is off.

By applying a predetermined first voltage to the gate electrode 53, thegate electrode 53 enters the on state. As shown in FIG. 10A, thepotential of the poly-Si island 52 decreases due to capacitive couplingwith the gate electrode 53. Since the insulating film 54 is set to 3 nmin which a tunneling current occurs and the poly-Si island 52 is set to5 nm smaller than the mean-free-path of an electron. The electronsinjected from the source 50 to the poly-Si island 52 flows into thedrain 51 almost without being scattered. When the potential of thesource 50 and that of the drain 51 become equal to each other, thechannel current reaches equilibrium, and a seeming channel current isstopped.

Subsequently, by applying a predetermined second voltage to the gateelectrode 53, the off state is obtained. As shown in FIG. 10B, thepotential in the poly-Si island 52 increases by the capacitive couplingwith the gate electrode 53. When seen from the source 50, a potentialbarrier is generated by the poly-Si island 52. In this case, by thepotential barrier, the leak current between the source 50 and the drain51 can be reduced to an extremely small value.

Although the gate electrode 53 is provided on the poly-Si island 52 viathe gate insulating film in the example, also by providing the gateelectrode 53 under the poly-Si island 52 via the gate insulating film,the characteristics of the switch do not change basically.

FIG. 11 is a sectional structural diagram showing an example of a pixelswitch for use in the image display device and a device as a componentof a gate-line driving circuit and a signal-line driving circuit. Sincethe configuration and operation of a TFT (Thin-Film-Transistor) liquidcrystal panel in the example are basically the same as those in theforegoing example, their description will not be repeated here.

The difference of the example of FIG. 11 from the foregoing example isthat the gate-line driving circuit CDV and the signal-line drivingcircuit DDV are constructed by using a poly-Si TFT provided on the sameglass substrate 60. It will be described by referring to FIG. 11.

FIG. 11 is a cross section illustrating the pixel switch and a poly-SiTFT as a representative component of the gate-line driving circuit CDVand the signal line driving circuit DDV provided on the glass substrate60. Although the pixel switch and the poly-Si TFT are not alwaysprovided adjacent to each other, for convenience of explanation, theyare arranged adjacent to each other. Since the configuration of thepixel switch has already been described in the foregoing example, thecorresponding components are designated by the same reference numeralsas those in the foregoing example and their description will not berepeated.

The poly-Si TFT is constructed by a source 61 obtained by doping ann-type impurity into a poly-Si thin film having a thickness of 50 nm, adrain 63, a channel region 62 of what is called an i-type in which noimpurity is doped, a gate insulating film 64 having a thickness of 20nm, and a gate electrode 65.

The poly-Si thin film constructing the source 61, drain 63, and channelregion 62 of the Si-TFT is fabricated in the same process as the poly-Sithin film constructing the drain 11 in the pixel switch. Similarly, thegate insulating film 64 is formed in the same process as the gateinsulating film 13 d, and the gate electrode 65 is formed in the sameprocess as the gate electrode 12.

Although the poly-Si TFT shown in FIG. 11 is of the n-type, in practice,a poly-Si TFT of the p-type having the same structure is also providedon the same glass substrate 60 as a component of a CMOS circuit.However, it is not shown here for simplicity of the drawing.

By using the configuration of the example, the liquid crystal TFT panelcan be easily realized without mounting an Si-LSI as a component of thegate-line driving circuit CDV and the signal-line driving circuit DDV asdescribed above. In particular, this is a great advantage in manufactureof a high-resolution TFT panel, in which it is difficult to mount anSi-LSI.

FIG. 12 is a sectional structural diagram showing another example of apixel switch for use in the image display device and a device as acomponent of the gate-line driving circuit and the signal-line drivingcircuit. Since the configuration and operation of a TFT liquid crystalpanel in the example are basically the same as those in the foregoingexample, their description will not be repeated here.

The difference of this example from the foregoing example is that thegate-line driving circuit CDV and the signal-line driving circuit DDVare constructed by using the same device as the pixel switch provided onthe same glass substrate 60. It will be described by referring to FIG.12.

FIG. 12 is a cross section illustrating a pixel switch similar to thatshown in FIG. 6 provided on the glass substrate 60 and a switch devicehaving the same configuration as a component of the gate-line drivingcircuit CDV and the signal line driving circuit DDV. Although the pixelswitch and the switch device are not always provided adjacent to eachother, for convenience of explanation, they are arranged adjacent toeach other. Since the configuration of the pixel switch has already beendescribed in the foregoing example, the corresponding components aredesignated by the same reference numerals as those in the foregoingembodiment and their description will not be repeated.

Since the structure and operation of the switch device having the samestructure as that as a component of the gate-line driving circuit CVDand the signal-line driving circuit DDV are the same as those of theabove-described device, each of components corresponding to those in theabove device is designated by the same reference numeral with “a”, andthe description will not be repeated.

Obviously, both the devices can be formed simultaneously in the sameprocess. However, with respect to the switch device having the samestructure as that of the switch device as a component of the gate-linedriving circuit CVD and the signal-line driving circuit DDV, accordingto a portion used in the circuit, the size on the layout is properlychanged, thereby adjusting the voltage-current conversion efficiency.

Although the device (switch device) shown in FIG. 12 is of the n-type,in practice, a device of the p-type having the same structure is alsoprovided on the same glass substrate 60, as a component of a CMOScircuit. However, it is not shown here for simplicity of the drawing.

By using the configuration of the example, the liquid crystal TFT panelcan be easily realized without mounting an Si-LSI in the same manner asthe first example. In the case of this example, all active devices canbe produced in the same process and there is an advantage such that thenumber of the processes can be reduced.

FIG. 13 is a sectional structural diagram of further another example ofthe switch device according to the invention. Since the configurationand operation of a TFT liquid crystal panel for which the switch devicein the example is used are basically the same as those in the foregoingexample, their description will not be repeated here. The difference ofthis example from the switch device shown in FIG. 1 is that the gateelectrode and the island layer are devised as follows.

In FIG. 13, the basic structure and operation of the switch device arethe same as those of the switch device in the example of FIG. 1, so thatthe corresponding components are designated by the same referencenumerals to each of which “b” is added and their description will not berepeated.

The difference of the structure of the switch device of the example fromthat of the switch device shown in FIG. 1 or 4 is that a gate electrode12 b and a poly-Si island 14 b construct a gate capacitor C1, and thegate electrode 12 b and a poly-Si island 15 b construct a gate capacitorC2. Specifically, in the switch device shown in FIGS. 1, 4, or the like,the poly-Si island 15 is not directly capacitive coupled with the gateelectrode 12 but is indirectly controlled by the gate electrode 12 viathe capacitive coupling (C1+C2) with the poly-Si island 14.

On the other hand, in the switch device of this example, the poly-Siislands 14 b and 15 b are directly controlled by the gate electrode 12 bvia the gate capacitors C1 and C2, so that the control on the channelcurrent by the gate voltage is improved, and the amplitude of the gatedriving voltage can be decreased. In other words, the parasitecapacitance C1 between the gate electrode 12 b and the upper poly-Siisland 14 b and the parasite capacitance C2 between the gate electrode12 b and the lower poly-Si island 15 b are constructed in a parallelform, so that the control on the channel current by the gate voltage canbe improved. In practice, a small parasitic capacitance exists betweeneach of the poly-Si islands 14 b and 15 b with another voltage node. Bycapacitance division with the parasite capacitance, the potential ofeach of the poly-Si islands 14 b and 15 b is determined. Consequently,by increasing the value of each of the parasitic capacitances C1 and C2with the gate electrode 12 b, the gate voltage can be transmitted to thepoly-Si islands 14 b and 15 b without a voltage loss.

FIG. 14 is a schematic circuit diagram showing an example of a dynamicRAM (hereinbelow, called a DRAM) using the switch device according tothe invention. FIG. 14 is a circuit diagram illustrating a simplifiedportion from address input to data output, while mainly showing a senseamplifier portion.

The DRAM of the example employs what is called a hierarchical word linesystem constructed by main word lines MWL and sub word lines SWL.Specifically, a circuit diagram shows that, as an example, a memoryarray is divided into a plurality of portions in the word line directionand the bit line direction, and is provided in a sense amplifier 160sandwiched by two sub arrays 150 in correspondence with the divided wordlines and bit lines and a cross area 180. The other components are shownas blocks.

A dynamic memory cell provided between the sub word line SWL and one,BL, of complementary bit lines BL and BLB in the sub array 150 isillustrated as a representative. The dynamic memory cell is constructedby an address selection switch Qm and a storage capacitor Cs.

As the address selection switch Qm, an MOSFET as in a conventionaldynamic RAM is not used but the switch device according to the inventionis used. Therefore, the address selection switch Qm is shown in a stripepattern so as to be discriminated from a normal MOSFET and so as toexpress that the channel portion between the source and drain has astack structure of the island layer and the insulating film. The gate ofthe switch device is connected to the sub word line SWL, the drain ofthe switch Qm is connected to the bit line BL, and the storage capacitorCs is connected to the source. The other electrode of the storagecapacitor Cs is shared and receives a plate voltage VPLT.

In the case of using the switch device as in the example, the stackedstructure is formed on the substrate and, moreover, the channel portioncan be easily formed with the stacked structure of the island layer andthe insulating film. Since a leak current hardly flows as describedabove, unlike the case of using a normal MOSFET having a source anddrain made by a diffusion layer on a silicon substrate, it isunnecessary to apply a negative back bias voltage VBB to the substrate(channel) in order to reduce the leak current. Thus, a reduced circuitscale and lower power consumption can be achieved. In the example, asMOSFETs other than the address selection switch Qm, MOSFETs formed onthe silicon substrate are used.

The selection level of the sub word line SWL is set to a high voltageVPP higher than the high level of the bit line only by a thresholdvoltage Vth of the address selection switch Qm in order to fully writean information voltage stored in a memory cell.

In the case of operating the sense amplifier by an inner-voltage dropVDP, the high level obtained by being amplified by the sense amplifierand supplied to the bit line is set to the inner voltage VDL level. Thehigh voltage VPP corresponding to the word line selection level istherefore set to VDL+Vth+α. A pair of complementary bit lines BL and BLBof the sub array provided on the left side in the sense amplifier aredisposed parallel to each other as shown in the drawing. Thecomplementary bit lines BL and BLB are connected to input and outputnodes of a unit circuit of the sense amplifier by shared switch MOSFETsQ1 and Q2.

The unit circuit of the sense amplifier is a CMOS latch circuitincluding N-channel type amplifier type MOSFETs Q5 and Q6 and P-channeltype amplifying type MOSFETs Q7 and Q8 whose gates and drains are crosscoupled in a latch form. The sources of the N-channel type MOSFETs Q5and Q6 are connected to a common source line CSN. The sources of theP-channel type MOSFETs Q7 and Q8 are connected to a common source lineCSP. To each of the common source lines CSN and CSP, a power switchMOSFET is connected. Although not limited, an operation voltagecorresponding to the ground potential is applied by an N-channel typepower switch MOSFET Q14 provided in the cross area 18 to the commonsource line CSN to which the sources of the N-channel type amplifyingMOSFETs Q5 and Q6 are connected.

Although not limited, to the common source line CSP to which the sourcesof the P-channel type amplifying MOSFETs Q7 and Q8 are connected, anN-channel type power MOSFET Q15 for over driving and an N-channel typepower MOSFET Q16 for supplying the inner voltage VDL are provided in thecross area 18. Although not limited, as the voltage for over driving,the source voltage VDD supplied from an external terminal is used.Alternately, in order to lessen the dependency on the source voltage VDDof the sense amplifier operation speed, the voltage may be slightlydropped to obtain the voltage from the source of the N-channel typeMOSFET having a gate to which VPP is applied and having a drain to whichthe source voltage VDD is supplied.

An activate signal SAP1 for sense amplifier overdriving to be suppliedto the gate of the N-channel type power MOSFET Q15 has the same phase asthat of an activate signal SAP2 to be supplied to the gate of theN-channel type MOSFET Q16. SAP1 and SAP2 are set to the high level in atime sequential manner. Although not limited, the high level of SAP1 andSAP2 is the high voltage VPP level. That is, by using the high voltageVPP, the N-channel type MOSFETs Q15 and Q16 can be sufficiently drivento the on state. After the MOSFET Q15 enters the off state (low level ofthe signal SAP1) and the MOSFET Q16 enters the on state (high level ofthe signal SAP2), a voltage corresponding to the inner voltage VDL canbe output from the source side.

The input and output nodes of the unit circuit of the sense amplifierare provided with a precharge (equalize) circuit constructed by anequalize MOSFET Q11 for short-circuiting the complementary bit lines andswitch MOSFETs Q9 and Q10 for supplying a half precharge voltage VBLR tothe complementary bit lines. A precharge signal PCB is commonly suppliedto the gates of the MOSFETs Q9 to Q11. An inverter circuit (not shown)is provided in the cross area to make a driver circuit for generatingthe precharge signal PCB rise or fall at high speed. Specifically, onstart of an access to a memory, prior to a word line selecting timing,the MOSFETs Q9 to Q11 constructing the precharge circuit are switched athigh speed via the inverter circuits provided so as to be spread in thecross areas.

In the cross area 180, an IO switch circuit IOSW (switch MOSFETs Q19 andQ20 for connecting a local IO and a main IO) is disposed. Further, inaddition to the circuits shown in FIG. 14, as necessary, a halfprecharge circuit of the common source lines CSP and CSN of the senseamplifier, a half precharge circuit of local input/output lines LIO, aVDL precharge circuit of main input/output lines, a distributed drivercircuit of shared selection signal lines SHR and SHL, and the like areprovided.

The sense amplifier unit circuit is connected to the complementary bitlines BL and BLB of the sub array 150 on the lower side of the drawingvia the shared switch MOSFETs Q3 and Q4. For example, when the sub wordline SWL in the upper sub array is selected, the upper-side sharedswitch MOSFETs Q1 and Q2 of the sense amplifier are turned on and thelower-side shared switch MOSFETs Q3 and Q4 are turned off. The switchMOSFETs Q12 and Q13 construct a column (Y) switch circuit which isturned on when the selection signal YS is set to the selection level(high level) to thereby connect the input and output nodes of the senseamplifier unit circuit to local input/output lines LIO1 and LIO1B, LIO2and LIO2B, and the like of the sense amplifier unit circuit.

Consequently, the input and output nodes of the sense amplifier areconnected to the upper-side complementary bit lines BL and BLB tothereby amplify a weak signal of a memory cell connected to the selectedsub word line SWL. The amplified signal is transmitted to the localinput/output lines LIO1 and LIO1B via the column switch circuit (Q12 andQ13). The local input/output lines LIO1 and LIO1B extend along the senseamplifier column, that is, in the lateral direction of the drawing. Thelocal input and output lines LIO1 and LIO1B are connected to maininput/output lines MIO and MIOB to which the input terminals of a mainamplifier 610 are connected via an IO switch circuit constructed by theN-channel type MOSFETs Q19 and Q20 provided in the cross area 180.

The IO switch circuit is switched by a selection signal generated bydecoding an X address signal. The IO switch circuit may have a CMOSswitch configuration in which a P-channel type MOSFET is connected inparallel with each of the N-channel type MOSFETs Q19 and Q20. In a burstmode of a synchronous DRAM, the column selection signal YS is switchedby a counter operation. Connection of the local input/output lines LIO1and LIO1B and LI02 and LIO2B and two pairs of complementary bit lines BLand BLB of the sub array is sequentially switched.

An address signal Ai is supplied to an address buffer 510. The addressbuffer time-divisionally drives to capture an X address signal and a Yaddress signal. The X address signal is supplied to a predecoder 520,and a selection signal of the main word line MWL is generated via a mainrow decoder 110 and a main word driver 120. Since the address buffer 510receives the address signal Ai supplied from the external terminal, itoperates on the source voltage VDD supplied from the external terminal.The predecoder also operates on the source voltage VDD, and the mainword driver 120 operates on the high voltage VPP for a conversion. Asthe main word driver 120, a logic circuit with a level shift functionfor receiving the predecoded signal is used. A column decoder (driver)530 receives the Y address signal supplied by time-divisional drive ofthe address buffer 510 and generates the selection signal YS.

The main amplifier 610 operates on the source voltage VDD, and a signalis output from an external terminal Dout via an output buffer 620operating on the source voltage VDD supplied from the external terminal.A write signal input from an external terminal Din is captured via aninput buffer 630 and is supplied to the main input/output lines MIO andMIOB via a write amplifier (writer driver) included in the mainamplifier 610 in the drawing. An input section of the output buffer 620is provided with a level shifter and a logic unit for outputting anoutput signal of the level shifter synchronously with a timing signalcorresponding to the clock signal.

Although not limited, the source voltage VDD supplied from the externalterminal is set to 3.3V in a first mode and the operation voltage VDL ofthe sense amplifier is set to 1.8V. The word line selection signal (highvoltage) is set to 3.6V. The precharge voltage VBLR for a bit line isset to 0.9V corresponding to VDL/2 and the plate voltage VPLT is alsoset to 0.9V. The source voltage VDD supplied from the external terminalmay be set to a low voltage such as 2.5 to 2V as a second mode. In thecase of such a low source voltage VDDQ, a low voltage VDL may be set tobe equal to the source voltage VDD.

The DRAM of the example is constructed by using, as the addressselection device, what is called a tunnel effect transistor according tothe invention as described above. With the configuration, a reduced leakcurrent is realized and a refresh rate can be increased. Even when analpha ray is irradiated and an electron-hole pair is generated in acell, the tunnel film serves as a stopper against the flow of electronand hole, so that the potential in the cell is not changed.Consequently, it is not impossible to make the DRAM operate as anonvolatile memory in theory. To a bit line, a source and draindiffusion layer connected as in the case where an address MOSFET is usedis not connected. The parasitic capacitance on the bit line can betherefore largely reduced, and a read voltage corresponding to readcharges from the memory cell scan be increased. Alternately, a number ofmemory cells can be connected to a single bit line.

Since the parasitic capacitance on the bit line to which a memory cellis connected decreases as described above, accordingly, the capacitancevalue of the capacitor for storing information in the memory cell can besmaller, so that a smaller cell size can be realized. Consequently, inthe same chip size, the number of storage bits can be increased.Further, by the reduction in the parasitic capacitance on the bit line,the load on the sense amplifier is lightened, so that high-speed readingoperation can be also realized and the refresh rate can be largelyincreased. By the synergy, lower power consumption can be realized.

It is also possible to use the switch device according to the inventionin place of the MOSFETs for the peripheral circuits such as the senseamplifier in a manner similar to the memory cell addresss electionswitch Qm. For an output buffer circuit as well, the same device as thatusing the switch device according to the invention is used. Since theimproved current driving capability can be realized by the device in theinvention, the output buffer circuit can be formed in a relatively smalldevice size.

According to the invention, therefore, the output buffer having highcurrent driving capability and a DRAM cell matrix designed at extremelyhigh packing density can be therefore manufactured in the same process.In this case, in place of the silicon substrate, a quartz substrate or asubstrate having excellent flatness can be used as a substrate as in anMOSFET.

In the case where storage charges in the storage capacitor are madenon-volatile due to reduction in the leak current of the switch device,strictly, the resultant is not a dynamic memory cell. However, since thedevice configuration of a memory cell constructed by the switch deviceand the storage capacitor is the same as that of a conventional dynamicmemory cell, the memory circuit using such a memory cell is called aDRAM in the specification for convenience.

The actions and effects of the examples are as described below.

(1) An effect such that a high-performance switch device can be obtainedis produced. In the switch device, a semiconductor island layer isformed on a first source and drain layer which is a conductive layer. Onand under the semiconductor island layer, first insulating films areformed. A second source and drain layer which is a conductive layer anda gate electrode which is made by a conductive layer are formed on thesemiconductor island layer via at least a second insulating film. In afirst mode, a first voltage is applied to the gate electrode, apotential corresponding to the first potential is applied to thesemiconductor island layer via parasitic capacitance formed by the gateelectrode and the semiconductor island layer to thereby increase thepotential, and a current is passed between the first and second sourceand drain layers along the direction of an electric field applied to theparasitic capacitance. In a second mode, a second voltage is applied tothe gate electrode, a potential corresponding to the second potential isapplied to the semiconductor island layer via the parasite capacitanceformed by the gate electrode and the semiconductor island layer tothereby decrease the potential, and a current is not substantiallypassed between the first and second source and drain layers.

(2) In the semiconductor island layer, a first surface portion providedin correspondence with the second source and drain layer and a secondsurface portion corresponding to the gate electrode are formed. Thefirst insulating film is formed on the first surface portion, and atleast the second insulating film is formed on the second surfaceportion. Consequently, an effect such that the voltage applied to thegate electrode can be efficiently transmitted to the semiconductorisland layer and the switch controllability can be increased isobtained.

(3) A plurality of the semiconductor island layers are formed andstacked along the current flowing direction, thereby obtaining an effectsuch that a leak current in the off state can be further reduced.

(4) In each of the plurality of semiconductor island layers, a firstsurface portion provided in correspondence with a semiconductor islandarea to be formed and a second surface corresponding to the gateelectrode are provided. The first insulating film is formed on the firstsurface portion, and at least the second insulating film is formed onthe second surface portion. Therefore, an effect such that while furtherreducing the leak current in the off state, the voltage applied to thegate electrode can be efficiently transmitted to the semiconductorisland layer, and the switch controllability can be increased isobtained.

(5) The first insulating film is constructed by a thin insulating filmthrough which a tunneling current flows, the semiconductor island layeris formed to have a thin thickness smaller than an electronmean-free-path, and the second insulating film is constructed by a thickinsulating film through which the tunneling current does not flow. Withthe configuration, an effect such that the operation current in the onstate can be increased and the leak current in the off state can bereduced can be obtained.

(6) By using the switch device as an address selection switch andallowing a signal electric carrier to be held in a capacitor via theswitch device, an effect such that a memory circuit having excellentdata retaining characteristic and excellent memory access characteristicfor reading/writing operation can be obtained is produced.

(7) In an image display device including pixel electrodes formed on aflat substrate and arranged in a matrix for forming a liquid-crystalcapacitor with a common electrode to which a predetermined voltage isapplied, a pixel switch provided for each of the pixel electrodesarranged in the matrix to write a display signal to the pixel electrode,write switch control means for controlling the pixel switch, and displaysignal input means for writing a display signal to a signal lineconnected to the pixel switch and provided for each column, in the pixelswitch, a semiconductor island layer is formed on the first source anddrain layer which is a conductive layer. On and under the first sourceand drain layer, first insulating films are formed. A second source anddrain layer which is a conductive layer and a gate electrode made by aconductive layer formed on the semiconductor island layer at least via asecond insulating film are formed. In a first mode, a first potential isapplied to the gate electrode, a potential corresponding to the firstpotential is applied to the semiconductor island layer via parasiticcapacitance formed by the gate electrode and the semiconductor islandlayer to thereby increase the potential, and a current is passed betweenthe first and second source and drain layers along the direction of anelectric field applied to the parasitic capacitance. In a second mode, asecond potential is applied to the gate electrode, a potentialcorresponding to the second potential is applied to the semiconductorisland layer via the parasitic capacitance formed by the gate electrodeand the semiconductor island layer to thereby decrease the potential,and a current is not substantially passed between the first and secondsource and drain layers. By using such a switch device, a load capacitorfor preventing flicker noise or the like caused by the leak currentbecomes unnecessary and the fill factor of pixels arranged at a highpacking density can be increased. Thus, an effect such that an operationof displaying a high-definition high-quality image can be performed isobtained.

(8) Each of the write switch control means and the image signal inputmeans is constructed by a single crystal silicon MOS transistor formedon the flat substrate. With the configuration, the display portion andthe driving circuit can be integrally formed. Thus, an effect such thatreduction in the number of assembling steps and higher definition can beeasily realized is obtained.

(9) Each of the write switch control means and the image signal inputmeans is constructed by a thin film MOS transistor formed on the flatsubstrate. With the configuration, the display portion and the drivingcircuit can be integrally formed by using the same process. Thus, aneffect such that reduction in the number of manufacturing steps and thenumber of assembling steps and higher definition can be easily realizedis obtained.

(10) In a method of manufacturing an apparatus including a switchdevice, a semiconductor island layer is formed on a first source anddrain layer which is a conductive layer. On and under the semiconductorisland layer, first insulating films are formed. A second source anddrain layer which is a conductive layer and a gate electrode which ismade by a conductive layer are formed on the semiconductor island layervia at least a second insulating film. In a first mode, a first voltageis applied to the gate electrode, a potential corresponding to the firstpotential is applied to the semiconductor island layer via parasiticcapacitance formed by the gate electrode and the semiconductor islandlayer to thereby increase the potential, and a current is passed betweenthe first and second source and drain layers along the direction of anelectric field applied to the parasitic capacitance. In a second mode, asecond voltage is applied to the gate electrode, a potentialcorresponding to the second potential is applied to the semiconductorisland layer via the parasite capacitance formed by the gate electrodeand the semiconductor island layer to thereby decrease the potential,and a current is not substantially passed between the first and secondsource and drain layers. In the method, each of the first and secondsource and drain layers is formed by depositing a polysilicon thin filmlayer to which a high-concentration impurity is doped by CVD. The firstinsulating film is formed by: a first step of sequentially stacking aninsulating film layer and an amorphous silicon film on the first orsecond source and drain layer or the semiconductor island layer; asecond step of irradiating the amorphous silicon film with a laser beamto thereby convert the amorphous silicon film into a polysilicon film;and a third step of stacking a thin insulating film on the polysiliconfilm. By the method, an effect such that the film thickness required foreach of the films can be excellently controlled even in a largesubstrate such as a liquid crystal panel.

(11) The first source and drain layer and the second source and drainlayer are sequentially stacked and patterned in a lump to thereby form achannel region of the switch device. Consequently, an effect such thatthe number of patterning steps can be reduced and a foreign matter canbe prevented from being adhered to each of the films in the patterningstep is produced.

(12) In an apparatus for manufacturing a device including a switchdevice, a semiconductor island layer is formed on a first source anddrain layer which is a conductive layer. On and under the semiconductorisland layer, first insulating films are formed. A second source anddrain layer which is a conductive layer and a gate electrode which ismade by a conductive layer are formed on the semiconductor island layervia at least a second insulating film. In a first mode, a first voltageis applied to the gate electrode, a potential corresponding to the firstpotential is applied to the semiconductor island layer via parasiticcapacitance formed by the gate electrode and the semiconductor islandlayer to thereby increase the potential, and a current is passed betweenthe first and second source and drain layers along the direction of anelectric field applied to the parasitic capacitance. In a second mode, asecond voltage is applied to the gate electrode, a potentialcorresponding to the second potential is applied to the semiconductorisland layer via the parasite capacitance formed by the gate electrodeand the semiconductor island layer to thereby decrease the potential,and a current is not substantially passed between the first and secondsource and drain layers. Each of the first and second source and drainlayers is formed by depositing a polysilicon thin film layer to which ahigh-concentration impurity is doped by CVD. The first insulating filmis formed by: a first step of sequentially stacking an insulating filmlayer and an amorphous silicon film on the first or second source anddrain layer or the semiconductor island layer; a second step ofirradiating the amorphous silicon film with a laser beam to therebyconvert the amorphous silicon film into a polysilicon film; and a thirdstep of stacking a thin insulating film on the polysilicon film. Themanufacturing apparatus is used for the above manufacturing method.Input/output ports of CVD systems corresponding to the steps and a laserexposure instrument are coupled to a common chamber so as to performprocesses continuously until the second source and drain film is stackedwithout substantially exposing the device to atmosphere. Thus, an effectsuch that each of the films can be manufactured with highcontrollability even on a large substrate such as a liquid crystal panelis obtained.

Although the invention achieved by the inventor herein has beenconcretely described on the basis of the examples, obviously, theinvention is not limited to the examples but can be variously modifiedwithin a range not departing from the gist. For example, any devicepattern of the switch device may be used as long as the stack structureas described above is used. To increase the capacitance value of theparasitic capacitance between the gate electrode and the island layer,it is also possible to remove the thin first insulating film in aportion overlapped with the gate electrode and form a relatively thicksecond insulating film. However, as described above, the firstinsulating film is much thinner than the second insulating layer.Consequently, even when the thickness of the second insulating film isdetermined on precondition of the first insulating film, a similareffect can be produced. The gate electrode may be formed on a flatsubstrate. Specifically, in FIG. 1, it is possible to arrange the sourceand drain SD1 and the gate electrode via an insulating film and, onthem, stack the first insulating film, the island layer, and the sourceand drain SD2. The switch device according to the invention can bewidely used for an image display panel and a memory circuit as describedabove and as a switch device.

Industrial Applicability

The invention can be widely applied to a semiconductor device includinga memory circuit in which a switch device is formed, an image displaydevice using the semiconductor device as a pixel switch, and method andapparatus for manufacturing the image display device.

What is claimed is:
 1. A semiconductor device comprising: a firstconductive layer which functions as a source or drain; a semiconductorisland layer formed over said first conductive layer, wherein a firstinsulating film is formed between said first conductive layer and saidsemiconductor island layer; a second conductive layer which functions asa source or drain formed over said semiconductor island layer, wherein asecond insulating film is formed between said second conductive layerand said semiconductor island layer; and a gate electrode which is aconductive layer formed over said semiconductor island layer on a gateinsulating film formed on said second insulating film, wherein in afirst mode in which a first potential is applied to said gate electrode,a potential corresponding to said first potential is applied to saidsemiconductor island layer via parasitic capacitance formed by said gateelectrode and said semiconductor island layer to thereby increase saidsemiconductor island layer potential, and a current is passed betweensaid first and second conductive layers through said semiconductorisland layer, said first insulating film and said second insulating filmalong a direction of an electric field applied between said gateelectrode and said semiconductor island area, and in a second mode inwhich a second potential is applied to said gate electrode, a potentialcorresponding to said second potential is applied to said semiconductorisland layer via a parasitic capacitance formed by said gate electrodeand said semiconductor island layer to thereby decrease saidsemiconductor island layer potential, and a current is substantiallyinhibited from passing between said first and second conductive layersthrough said semiconductor island layer, said first insulating film andsaid second insulating film.
 2. The semiconductor device according toclaim 1, wherein said semiconductor island layer has a first surfaceportion and a second surface portion on a same plane, wherein said firstsurface portion is in register with a portion of said second conductivelayer and said a second surface portion is in register with a portion ofsaid gate electrode, said second insulating film is formed on at leastsaid first surface portion, and at least a portion of said gateinsulating film is formed in register with said second surface portion.3. The semiconductor device according to claim 1, wherein a plurality ofsaid semiconductor island layers are formed by being stacked along saiddirection of said electric field.
 4. The semiconductor device accordingto claim 3, wherein a semiconductor island layer of said plurality ofsemiconductor island layers is positioned closest to said secondconductive layer and said gate electrode and has a first surface portionin register with a portion of said second semiconductor layer and asecond surface portion in register with a portion of said gateelectrode, said second insulating film is formed on at least said firstsurface portion, and at least a portion of said gate insulating film isformed in register with on said second surface portion.
 5. Thesemiconductor device according to claim 1, wherein said first and secondinsulating films are thin insulating films through which a tunnelingcurrent can flow, said semiconductor island layer has a thickness lessthan an electron mean free path therein, and said gate insulating filmis a thick insulating film through which no substantial tunnelingcurrent can flow.
 6. The semiconductor device according to claim 5,wherein said first conductive layer of said semiconductor device isconnected to a bit line extended in a first direction, and said secondconductive layer is connected to one electrode of a storage capacitor tothe other electrode of which a predetermined potential is applied, andsaid gate electrode is connected to a word line extended in a seconddirection orthogonal to said bit line and serves as a component of amemory cell.
 7. An image display device comprising pixel electrodesformed on a flat substrate and arranged in a matrix for forming aliquid-crystal capacitor with a common electrode formed to which apredetermined voltage is applied, a pixel switch provided for each ofsaid pixel electrodes arranged in the matrix to write a display signalto said pixel electrode, write switch control means for controlling saidpixel switch, a signal line connected to said pixel switch and providedfor each column, and display signal input means for writing a displaysignal onto said signal line, wherein said pixel switch comprises: afirst conductive layer which functions as a source or drain and isformed on a surface of said flat substrate and connected to said signalline; a semiconductor island layer formed over said first conductivelayer, wherein a first insulating film is formed between said firstconductive layer and said semiconductor island layer; a secondconductive layer which functions as a source or drain formed over saidsemiconductor island layer and connected to said pixel electrode,wherein a second insulating film is formed between said secondconductive layer and said semiconductor island layer; and a gateelectrode which is a conductive layer formed over said semiconductorisland layer on a gate insulating film formed on said second insulatingfilm, and is connected to said write switch control means, wherein in afirst mode in which a first potential is applied to said gate electrodeby said write switch control means, a potential corresponding to saidfirst potential is applied to said semiconductor island layer viaparasitic capacitance formed by said gate electrode and saidsemiconductor island layer to thereby increase said semiconductor islandlayer potential, and a current is passed between said first and secondconductive layers through said semiconductor island layer, said firstinsulating film and said second insulating film along a direction of anelectric field applied between said gate electrode and saidsemiconductor island layer, and in a second mode in which a secondpotential is applied to said gate electrode by said write switch controlmeans, a potential corresponding to said second potential is applied tosaid semiconductor island layer via the parasitic capacitance formed bysaid gate electrode and said semiconductor island layer to therebydecrease said semiconductor island layer potential, and a current issubstantially inhibited from passing between said first and secondconductive layers through said semiconductor island layer, said firstinsulating film and said second insulating film.
 8. The image displaydevice according to claim 7, wherein each of said write switch means andsaid image signal input means is constructed by a single crystal siliconMOS transistor formed on said flat substrate.
 9. The image displaydevice according to claim 7, wherein each of said write switch means andsaid image signal input means is constructed by a thin film MOStransistor formed on said flat substrate.
 10. A method of manufacturinga switch device comprising: a first step of forming a first layer ofpolycrystalline silicon on a substrate, said first polycrystalline layerbeing conductive and doped with an impurity; a second step of forming afirst thin insulating film on said first polycrystalline silicon layer;a third step of forming an amorphous silicon layer on said first thininsulating film and then irradiating said amorphous silicon layer with alaser beam to thereby convert said amorphous silicon layer into a secondpolycrystalline silicon layer; a fourth step of forming a second thininsulating film on said second polycrystalline silicon layer; a fifthstep of forming a third polycrystalline silicon layer on said secondthin insulating film, said third polycrystalline silicon layer beingconductive and doped with an impurity; a sixth step of patterning saidfirst polycrystalline silicon layer, said first thin insulating film,said second polycrystalline silicon layer, said second insulating filmand said third polycrystalline silicon layer by dry etching using asingle mask; a seventh step of removing part of said thirdpolycrystalline silicon layer to expose at least a portion of saidsecond thin insulating film; an eighth step of forming a gate insulatingfilm on said exposed portion of said second thin insulating film; and aninth step of forming a gate electrode on said gate insulating film. 11.The method of manufacturing a switch device according to claim 10,wherein each of said first and second thin insulating films is a siliconnitride film.
 12. The semiconductor device according to claim 4, whereinsaid first and second insulating films are thin insulating films throughwhich a tunneling current can flow, said semiconductor island layer hasa thickness less than an electron mean free path therein, and said gateinsulating film is a thick insulating film through which no substantialtunneling current can flow.
 13. The semiconductor device according toclaim 12, wherein said first conductive layer of said semiconductordevice is connected to a bit line extended in a first direction, andsaid second conductive layer is connected to one electrode of a storagecapacitor to the other electrode of which a predetermined potential isapplied, and said gate electrode is connected to a word line extended ina second direction orthogonal to said bit line and serves as a componentof a memory cell.